From: Peter Ashenden (firstname.lastname@example.org)
Date: Tue Jul 06 2004 - 22:07:18 PDT
That is a good point, and one that needs to be addressed in the near future.
Given that the SV-WG has only just been established and we've only just got
DASC-SC approval for the revised 1364 PAR, it is early days still.
I have, however, already raised the issue with the SV-WG Chair, asking him
to consider how work on P1364 might be structured. I will also liaise with
the P1364 Chair on this.
-- Dr. Peter J. Ashenden email@example.com Ashenden Designs Pty. Ltd. www.ashenden.com.au PO Box 640 Ph: +61 8 8339 7532 Stirling, SA 5152 Fax: +61 8 8339 2616 Australia Mobile: +61 414 70 9106
> -----Original Message----- > From: firstname.lastname@example.org > [mailto:email@example.com] On Behalf Of > Shalom.Bresticker@freescale.com > Sent: Tuesday, 6 July 2004 23:20 > To: Peter Ashenden > Cc: firstname.lastname@example.org > Subject: RE: /bbs/pub/dasc/dasc-sc-list: DASC-SC: result of > vote on 1364 PAR > > > Thank you, Peter. > > However, there is still no communcations channel between the > SV-WG and the P1364 WG. > > Shalom > > > On Tue, 6 Jul 2004, Peter Ashenden wrote: > > > Dear colleagues, > > > > Shalom has forwarded my message from the DASC-SC list to this list > > without comments, so please let me add some context. > > > > The revised PAR provides for the 1364 project to migrate to the > > SystemVerilog Working Group (SV-WG). As I outlined in my > accomanying > > note to IEEE RevCom, this will allow for coordination of > corrections > > to the Verilog standard with fast-tracked standardization of the > > SystemVerilog specification. Work can also proceed within > the SV-WG > > toward a merger of the two specifications to form a single > standard, > > and on development of subsequent enhancements using the > work done to > > date in the 1364 WG. > > > > At the inaugural meeting of the SV-WG last week, the proposed WG > > procedures document was reviewed and adopted. On my request, the > > proposed procedures included a clause providing for subgroups to be > > created with voting rights granted to WG observers. The WG adopted > > this clause, specifically noting (as recorded in the draft minutes): > > > > It is understood ... that while the Working Group is > entity based, > > individual experts may > > be allowed by the Working Group to have individual > voting rights > > in sub-working groups. > > > > The rationale is that many individual members of the IEEE > P1364 WG and > > the Accellera SystemVerilog WG have made significant and valuable > > contributions, and that their continued contributions are > encouraged. > > I hope that P1364 WG members will recognize this as > evidence that they > > are not being frozen out of participation. > > > > Thanks, and best regards, > > > > Peter Ashenden > > DASC Chair > > > > -- > > Dr. Peter J. Ashenden email@example.com > > Ashenden Designs Pty. Ltd. www.ashenden.com.au > > PO Box 640 Ph: +61 8 8339 7532 > > Stirling, SA 5152 Fax: +61 8 8339 2616 > > Australia Mobile: +61 414 70 9106 > > -- > Shalom Bresticker Shalom.Bresticker > @freescale.com > Design & Reuse Methodology Tel: > +972 9 9522268 > Freescale Semiconductor Israel, Ltd. Fax: > +972 9 9522890 > POB 2208, Herzlia 46120, ISRAEL Cell: > +972 50 5441478 > > [ ]Freescale Internal Use Only > [ ]Freescale Confidential Proprietary >
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