From: Charles Dawson (chas@cadence.com)
Date: Mon Jan 26 2004 - 08:50:30 PST
AGENDA
1. Review minutes from last meeting (1/12/2004)
2. Review Patent information
Go to:
http://www.verilog.com/1364donations.html
and click on patent policy.
3. Liaisons
- Francoise to report on BTF.
- Steve to report on Encryption sub-committee to BTF.
4. New business
- Chas to get Tapati on appropriate email aliases.
- Chas to send corrected diagram for PTF 71 to Shalom.
- PTF 366.
- Others?
5. Review old business:
- Chas/Stu to enter Stu's PTF items into database.
- Chas to work on proposal for PTF 342.
- Steve to compare BNF with the access available
for attributes to see if they match
- Chas to write up a final proposal for PTF 341.
- Chas to write up new proposal for PTF 120.
- Francoise to talk with the IEEE editor about UML.
- Francoise to remove "+" from tags in UML diagrams and
add vpi prefix where appropriate.
- Francoise to send out HTML for 1364-2001 diagrams, using
something other than JPG for importing diagrams into frame.
- Stu to write proposal for PTF 368.
- Francoise to write proposals for PTF 284, 373, 374, and 396.
- Steve to write proposals for PTF 286, 311, 397, and 495.
- Nish to write proposals for PTF 307, 312, 313, and 365.
- Francoise to write a new proposal for PTF 398,
eliminating bit selects and using the "whose parent is an
array" terminology.
- Nish to determine if callbacks described in PTF 312 have
been implemented in VCS.
- Nish to determine if access to memories have been
implemented in VCS.
- Stu to send PDF of document for PTF 312.
- ALL to review documents from the BTF sent on 12/15/2003.
- Chas to send corrected diagram for PTF 71 to Shalom.
- Chas to ask if vpiMultiArray has been implemented in VCS
and MTI.
- Nish to transition all action items to Tapati.
- All to review Generates proposal from ETF committee.
- Chas to verify it is okay to change direction for PTF 366.
- Tapati to review proposal for PTF 516.
6. Review PTF items with proposals:
- PTF 341
- PTF 397
- PTF 398
- PTF 516
-- Charles Dawson Senior Engineering Manager NC-Verilog Team Cadence Design Systems, Inc. 270 Billerica Road Chelmsford, MA 01824 (978) 262 - 6273 chas@cadence.com
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