PTF agenda for 5/3/2004

From: Charles Dawson (chas@cadence.com)
Date: Mon May 03 2004 - 07:26:46 PDT

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    AGENDA

    1. Review minutes from last meeting (4/5/2004)
    2. Review Patent information

       Go to:
         http://www.verilog.com/1364donations.html
       and click on patent policy.

    3. Liaisons

       - Anyone care to make a report?

    4. New business

       - Francoise to write a new proposal for PTF 398.
       - PTF 517
       - Others?

    5. Review old business:

       - Chas/Stu to enter Stu's PTF items into database.
       - Steve to compare BNF with the access available
         for attributes to see if they match
       - Chas to write up new proposal for PTF 120.
       - Francoise to remove "+" from tags in UML diagrams and
         add vpi prefix where appropriate.
       - Francoise to send out HTML for 1364-2001 diagrams, using
         something other than JPG for importing diagrams into frame.
       - Stu to write proposal for PTF 368.
       - Francoise to write proposals for PTF 373, 374, and 396.
       - Steve to write proposals for PTF 286, 311, and 495.
       - Tapati to write proposals for PTF 307, 312, and 313.
       - Francoise to write a new proposal for PTF 398.
       - All to review Generates proposal from ETF committee.
       - Francoise, et all to review BTF generates proposal
         for the upcoming vote, with particular emphasis on
         how we will address generates in VPI.
       - Stu to enter new PTF item for save/restart/reset issue.
       - Jim to write proposals for PTF 517, 518, 533, and 534.
       - Chas to write proposal for PTF 296.
       - Stu to write an addition to the proposal for PTF 342.
         This will cover that PLI 1.0 was deprecated in section 20
         and include some of the stuff currently in section 21
         (like the descriptions for the checktf and calltf).
       - Chas to try out example in PTF 329.

    6. Review PTF items with proposals:

       - PTF 320
       - PTF 524
       - PTF 525 

    -- 
Charles Dawson
Senior Engineering Manager
NC-Verilog Team
Cadence Design Systems, Inc.
270 Billerica Road
Chelmsford, MA  01824
(978) 262 - 6273
chas@cadence.com

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